The formation of electrical contacts to electronic and memory devices is a considerable challenge as a consequence of technology scaling, especially as pitch is reduced. In conventional methods for forming self-aligned contacts, formation of the contact area by a dry etching process of an oxide, such as reactive ion etching (RIE), causes unwanted removal of spacer, hard mask and silicide regions. Given recent and anticipated pitch scaling resulting in increasingly smaller pitches between gate structures, it has become increasingly difficult to prevent spacer loss when forming the contact areas. In addition, the difficulty is increased when etching processes have low etch selectivity with respect to the spacers formed along the gate structures (e.g., little or no etch selectivity between contact area oxide and nitride spacer). As a result, there is unwanted spacer, hard mask and silicide loss when forming the contact area vias, resulting in gate to source/drain shorts when the spacer and silicide are removed by the etching process. Moreover, the combination of contact area misalignment and the RIE issues can cause high gate leakage and low yield.
Accordingly, there is a need for a process that is capable of making suitable contacts which are self-aligned to the source and drain, and avoids unwanted shorts.